Quantum error correction below the surface code threshold (2024)

I Introduction

Although achieving below-threshold physical error rates is itself a formidable challenge, fault-tolerant quantum computing also imposes requirements beyond raw performance.These include features like stability over the hours-long timescales of quantum algorithms[21] and the active removal of correlated error sources like leakage[22].Fault-tolerant quantum computing also imposes requirements on classical coprocessors – namely, the syndrome information producedby the quantum device must be decoded as fast as it is generated[23].The fast operation times of superconducting qubits, rangingfrom tens to hundreds of nanoseconds, provide an advantage in speed but also a challenge for decoding errorsboth quickly and accurately.

In this work, we realize surface codes operating below threshold on two superconducting processors.Using a 72-qubit processor, we implement a distance-5 surface code operating with an integrated real-time decoder.In addition, using a 105-qubit processor with similar performance, we realize a distance-7 surface code.These processors demonstrate $\Lambda>2$ up to distance-5 and distance-7, respectively.Our distance-5 quantum memories are beyond break-even, with distance-7 preserving quantum information for more than twice as long as its best constituent physical qubit.To identify possible logical error floors, we also implement high-distance repetition codes on the 72-qubit processor, with error rates that are dominated by correlated error events occurring once an hour.These errors, whose origins are not yet understood, set a current error floor of $10^{-10}$.Finally, we show that we can maintain below-threshold operation on the 72-qubit processor even when decoding in real time, meeting the strict timing requirements imposed by the processor’s fast 1.1 µs cycle duration.

II A Surface code memory below threshold

We begin with results from our 105-qubit processor depicted in Fig.1a.It features a square grid of superconducting transmon qubits[25] with improved operational fidelities compared to our previously reported processors[26, 17].The qubits have a mean operating $T_{1}$ of 68 µs and $T_{2,\text{CPMG}}$ of 89 µs, which we attribute to improved fabrication techniques, participation ratio engineering, and circuit parameter optimization.Increasing coherence contributes to the fidelity of all of our operations which are displayed in Fig.1b.

We also make several improvements to decoding, employing two types of offline high-accuracy decoders.One is a neural network decoder[27], and the other is a harmonized ensemble[28] of correlated minimum-weight perfect matching decoders[29] augmented with matching synthesis[30].These run on different classical hardware, offering two potential paths towards real-time decoding with higher accuracy.To adapt to device noise, we fine-tune the neural network with processor data[27] and apply a reinforcement learning optimization to the matching graph weights[31].

We operate a distance-7 surface code memory comprising 49 data qubits, 48 measure qubits, and 4 additional leakage removal qubits, following the methods in Ref.[17].Summarizing, we initiate surface code operation by preparing the data qubits in a product state in either the $X_{L}$ or $Z_{L}$ basis of the ZXXZ surface code[32].We then repeat a variable number of cycles of error correction, during which measure qubits extract parity information from the data qubits to be sent to the decoder.Following each syndrome extraction, we run data qubit leakage removal (DQLR)[33] to ensure that leakage to higher states is short-lived.We measure the state of the logical qubit by measuring the individual data qubits and then check whether the decoder’s corrected logical measurement outcome agrees with the initial logical state.

From surface code data, we can characterize the physical error rate of the processor using the bulk error detection probability[34].This is the proportion of weight-4 stabilizer measurement comparisons that detect an error.The surface code detection probabilities are $p_{\text{det}}=(7.7\%,8.5\%,8.7\%)$ for $d=(3,5,7)$.We attribute the increase in detection probability with code size to finite size effects[24] and parasitic couplings between qubits.We expect both effects to saturate at larger processor sizes[35].

We characterize our surface code logical performance by fitting the logical error per cycle $\varepsilon_{d}$ up to 250 cycles, averaged over the $X$ and $Z$ bases.We average the performance of 9 different distance-3 subgrids and 4 different distance-5 subgrids to compare to the distance-7 code.Finally, we compute the error suppression factor $\Lambda$ using linear regression of $\ln(\varepsilon_{d})$ versus $d$.With our neural network decoder, we observe$\Lambda=2.14\pm 0.02$ and $\varepsilon_{7}$ = $(1.43\pm 0.03)\times 10^{-3}$(see Fig.1c-d).With ensembled matching synthesis, we observe$\Lambda=2.04\pm 0.02$ and $\varepsilon_{7}$ = $(1.71\pm 0.03)\times 10^{-3}$.

Furthermore, we simulate logical qubits of higher distances using a noise model based on the measured component error rates in Fig.1b, additionally including leakage and stray interactions between qubits[17, 24].These simulations are shown alongside the experiment in the inset of Fig.1d, both decoded with ensembled matching synthesis.We observe reasonable agreement with experiment and decisive error suppression, affirming that the surface codes are operating below threshold.

Thus far, we have focused on the error suppression factor $\Lambda$, since below threshold performance guarantees that physical qubit lifetimes and operational fidelities can be surpassed with a sufficiently large logical qubit.In fact, our distance-7 logical qubit already has more than double the lifetime of its constituent physical qubits.While comparing physical and logical qubits is subtle owingto their different noise processes, we plot a direct comparison between logical error rate and physical qubit error rate averaged over $X$ and $Z$ basis initializations in Fig.1c.To quantify qubit lifetime itself, we average uniformly over pure states using the metric proposed in Refs.[16, 24].The distance-7 logical qubit lifetime is $291\pm 6$ µs, exceeding the lifetimes of all the constituent physical qubits (median $85\pm 7$ µs, best $119\pm 13$ µs) by a factor of $2.4\pm 0.3$.Our logical memory beyond break-even extends previous results using bosonic codes[36, 37, 16] to multi-qubit codes, and it is a critical step toward logical operation break-even.

III Logical error sensitivity

Equipped with below-threshold logical qubits, we can now probe the sensitivity of logical error to various error mechanisms in this new regime.We start by testing how logical error scales with physical error and code distance.As shown in Fig.2a, we inject coherent errors with variable strength on both data and measure qubits, and extract two quantities from each injection experiment.First, we use detection probability as a proxy for the total physical error rate.Second, we infer the logical error per cycle by measuring logical error probability at 10 cycles, decoding with correlated matching[29].

In Fig.2b, we plot logical error per cycle versus detection probability for the distance-3, -5, and -7 codes.We find that the three curves cross near a detection probability of 20%, roughly consistent with the crossover regime explored in Ref.[17].The inset further shows that detection probability acts as a good proxy for $1/\Lambda$.When fitting power laws below the crossing, we observe approximately 80% of the ideal value $(d$$+$$1)/2$ predicted by Eq.1.We hypothesize that this deviation is caused by excess correlations in the device.Nevertheless, higher distance codes show faster reduction of logical error, realizing the characteristic threshold behavior in situ on a quantum processor.

To quantify the impact of correlated errors along with more typical gate errors, we form an error budget.Following the method outlined in Refs.[17, 38], we estimate the relative contribution of different component errors to $1/\Lambda$.We run simulations based on a detailed model of our 72-qubit processor.The model includes local noise sources due to gates and measurements, as well as two sources of correlated error: leakage, and stray interactions during our CZ gates which can induce correlated $ZZ$ and swap-like errors[24].Fig.2c shows our estimated error budget for $1/\Lambda$ in the 72-qubit processor when decoding with correlated matching.Applying the same decoder to experimental data,the error budget overpredicts $\Lambda$ by 20%, indicating that most but not all error effects in our processor have been captured.Correlated errors make up an estimated 17% of the budget, and while not a dominant contributor, we expect their importance to increase as error rates decrease.Overall, both local and correlated errors from CZ gates are the largest contributors to the error budget.Consequently, continuing to improve both coherence and calibration will be crucial to further reducing logical error.

One potential source of excess correlations that we actively mitigate is leakage to higher excited states of our transmon qubits.During logical qubit operation, we remove leakage from measure qubits using multi-level reset.For data qubits, DQLR swaps leakage excitations to measure qubits (or additional leakage removal qubits)[33].To examine sensitivity to leakage, we measure logical error probability of distance-3 and distance-5 codes in our 72-qubit processor with and without DQLR, with the results shown in Fig.2d.While activating DQLR does not strongly affect distance-3 performance, it substantially boosts distance-5 performance, resulting in a 35% increase in $\Lambda$.Comparatively, the detection probability decreases by only 12%[24], indicating that detection probability is only a good proxy for logical error suppression if errors are uncorrelated.Overall, we find that addressing leakage is crucial to operating surface codes with transmon qubits[39, 15, 33].

Finally, we test sensitivity to drift.Using our 72-qubit processor, we measure logical performance of one distance-5 and four distance-3 codes 16 times over 15 hours, with the results shown in Fig.2e.Prior to the repeated runs, we employ a frequency optimization strategy which forecasts defect frequencies of two-level systems (TLS).This helps to avoid qubits coupling to TLSs during the initial calibration as well as over the duration of the experiments.Additionally, between every four experimental runs, we recalibrate the processor to account for potential qubit frequency and readout signal drift.We observe an average $\Lambda=2.18\pm 0.07$ (standard deviation) and best $\Lambda=2.31\pm 0.02$[24] when decoding with the neural network.While the performance of the worst distance-3 quadrant appears to fluctuate due to a transient TLS moving faster than our forecasts, this fluctuation is suppressed in the distance-5 code, suggesting that larger codes are less sensitive to component-level fluctuations.Additionally, the logical error rates of experiments right after drift recalibration are not appreciably lower than those just prior, indicating that our logical qubit is robust to the levels of qubit frequency and readout drift present.These results show that superconducting processors can remain stable over the hours-long timescales required for large scale fault-tolerant algorithms[21].

IV Probing the ultra-low error regime with repetition codes

Despite realizing below-threshold surface codes, orders of magnitude remain between present logical error rates and the requirements for practical quantum computation.In previous work running repetition codes, we found that high-energy impact events occurred approximately once every 10 seconds, causing large correlated error bursts which manifested a logical error floor around $10^{-6}$[17].Such errors would block our ability to run error-corrected algorithms in the future, motivating us to reassess repetition codes on our newer devices.

Using our 72-qubit processor, we run a distance-29 repetition code for 1000 cycles of error correction over $2\times 10^{7}$ shots split evenly between bit- and phase-flip codes.In total, we execute $2\times 10^{10}$ cycles of error correction comprising 5.5 hours of processor execution time.Given the logical error probability $p_{L}$ at 1000 cycles, we infer the logical error per cycle as $\varepsilon_{d}=\frac{1}{2}\left(1-(1-2p_{L})^{1/1000}\right)$.To assess how the logical error per cycle scales with distance-$d$, we follow Ref.[38] and subsample lower distance repetition codes from the distance-29 data.

Averaging over bit- and phase-flip repetition codes, we obtain an error suppression factor $\Lambda=8.4\pm 0.1$ when fitting logical error per cycle versus code distance between $d=5$ and 11, as shown in Fig.3a.Notably, the error per cycle is suppressed far below $10^{-6}$, breaking past the error floor observed previously.We attribute the mitigation of high-energy impact failures to gap-engineered Josephson junctions[40].However, at code distances $d\geq 15$, we observe a deviation from exponential error suppression at high distances culminating in an apparent logical error floor of $10^{-10}$.Although we do not observe any errors at distance-29, this is likely due to randomly decoding correctly on the few most damaging error bursts.While this logical error per cycle might permit certain fault-tolerant applications[11], it is still many orders of magnitude higher than expected and precludes larger fault-tolerant circuits[21, 12].

When we examine the detection patterns for these high-distance logical failures, we observe two different failure modes.The first failure mode manifests as one or two detectors suddenly increasing in detection probability by over a factor of 3, settling to their initial detection probability tens or hundreds of cycles later[24].These less damaging failures could be caused by transient TLS’s appearing near the operation frequencies of a qubit, or by coupler excitations, but might be mitigated using methods similar to Refs.[39, 41].The second and more catastrophic failure mode manifests as many detectors experiencing a larger spike in detection probability simultaneously; an example is shown in Fig.3d.Notably, these anisotropic error bursts are spatially localized to neighborhoods of roughly 30 qubits (see inset).Over the course of our $2\times 10^{10}$ cycles of error correction, our processor experienced six of these large error bursts, which are responsible for the highest-distance failures.These bursts, such as the event shown in Fig.3d, are different from previously observed high-energy impact events[17].They occur approximately once an hour, rather than once every few seconds, and they decay with an exponential time constant around 400 µs, rather than tens of milliseconds.We do not yet understand the cause of these events, but mitigating them remains vital to building a fault-tolerant quantum computer.These results reaffirm that long repetition codes are a crucial tool for discovering new error mechanisms in quantum processors at the logical noise floor.

Furthermore, while we have tested the scaling law in Eq.1 at low distances, repetition codes allow us to scan to higher distances and lower logical errors.Following a similar coherent error injection method as in the surface code, we show the scaling of logical error versus physical error and code distance in Fig.3b-c, observing good agreement with $O(p^{(d+1)/2})$ error suppression.For example, reducing detection probability by a factor of 2 manifests in a factor of 250 reduction in logical error at distance-15, consistent with the expected $O(p^{8})$ scaling.This shows the dramatic error suppression that should eventually enable large scale fault-tolerant quantum computers, provided we can reach similar error suppression factors in surface codes.

V Real-time decoding

In addition to a high-fidelity processor, fault-tolerant quantum computing also requires a classical coprocessor that can decode errors in real time.This is because some logical operations are non-deterministic; they depend on logical measurement outcomes that must be correctly interpreted on the fly[23].If the decoder cannot process measurements fast enough, an increasing backlog of syndrome information can cause an exponential blow-up in computation time.Real-time decoding is particularly challenging for superconducting processors due to their speed.The throughput of transmitting, processing, and decoding the syndrome information in each cycle must keep pace with the fast error correcting cycle time of 1.1 µs.Using our 72-qubit processor as a platform, we demonstrate below-threshold performance alongside this vital module in the fault-tolerant quantum computing stack.

Our decoding system begins with our classical control electronics, where measurement signals are classified into bits then transmitted to a specialized workstation via low-latency Ethernet.Inside the workstation, measurements are converted into detections and then streamed to the real-time decoding software via a shared memory buffer.We employ a specialized version of the Sparse Blossom algorithm[42] optimized to quickly resolve local configurations of errors common in surface code decoding, using a parallelization strategy similar to Ref.[43].The decoder operates on a constant-sized graph buffer which emulates the section of the error graph being decoded at any instant, but which does not grow with the total number of cycles used in the experiment.Different threads are responsible for different spacetime regions of the graph, processing their requisite syndrome information as it is streamed in[44, 45, 43, 46].These results are fused until a global minimum-weight perfect matching is found.The streaming decoding algorithm is illustrated in Fig.4a-b.We also use a greedy edge reweighting strategy to increase accuracy by accounting for correlations induced by $Y$-type errors[29, 47].

In Fig.4d, we report the decoder latency, which we define as the time between the decoding software receiving the final cycle of syndrome measurements and the time when the decoder returns its correction.For our distance-5 surface code, we test different problem sizes by increasing the number of error correction cycles up to $10^{6}$.We observe that the average latency remains roughly constant at a net average of $63\pm 17$ µs independent of the length of the experiment (up to 1.1 seconds), indicating that the decoding problem is being processed in real time.This latency will eventually determine the reaction time of the logical processor when enacting non-Clifford gates, but does not yet include feedback into the logical circuit.

Importantly, we are able to maintain below-threshold performance even under the strict timing requirements imposed by real-time decoding.We run a dedicated experiment on our 72-qubit processor to compare real-time decoding to high-accuracy offline neural network decoding of the same data, with the results shown in Fig.4c.Our real-time decoder achieves $\varepsilon_{5}=0.35\%\pm 0.01\%$ and $\Lambda=2.0\pm 0.1$ using a device-data-independent prior.Meanwhile, the neural network decoder achieves $\varepsilon_{5}=0.269\%\pm 0.008\%$ and $\Lambda=2.18\pm 0.09$ when later decoding offline.The modest reduction in accuracy when comparing the real-time decoder to an offline decoder is expected as the real-time decoder must operate significantly faster.It requires a throughput of less than 1.1 µs per cycle compared to the neural network’s 24  µs per cycle[27].However, we do expect that many of our high-accuracy decoding methods can eventually be made real-time by introducing techniques like layered or windowed decoding[44, 45, 28].

VI Outlook

In this work, we have demonstrated a below-threshold surface code memory.Each time the code distance increases by two, the logical error per cycle is reduced by more than half, culminating in a distance-7 logical lifetime more than double its best constituent physical qubit lifetime.This signature of exponential logical error suppression with code distance forms the foundation of running large scale quantum algorithms with error correction.

Our error-corrected processors also demonstrate other key advances towards fault-tolerant quantum computing.We achieve repeatable performance over several hours and run experiments up to $10^{6}$ cycles without deteriorating performance, both of which are necessary for future large scale fault-tolerant algorithms.Furthermore, we have engineered a real-time decoding system with only a modest reduction in accuracy compared to our offline decoders.

Even so, many challenges remain ahead of us.Although we might in principle achieve low logical error rates by scaling up our current processors, it would be resource intensive in practice.Extrapolating the projections in Fig.1d, achieving a $10^{-6}$ error rate would require a distance-27 logical qubit using 1457 physical qubits.Scaling up will also bring additional challenges in real-time decoding as the syndrome measurements per cycle increase quadratically with code distance.Our repetition code experiments also identify a noise floor at an error rate of $10^{-10}$ caused by correlated bursts of errors.Identifying and mitigating this error mechanism will be integral to running larger quantum algorithms.

However, quantum error correction also provides us exponential leverage in reducing logical errors with processor improvements.For example, reducing physical error rates by a factor of two would improve the distance-27 logical performance by four orders of magnitude, well into algorithmically-relevant error rates[11, 12].We further expect these overheads will reduce with advances in error correction protocols[48, 49, 50, 51, 52, 53, 54] and decoding[55, 56, 57].

The purpose of quantum error correction is to enable large scale quantum algorithms.While this work focuses on building a robust memory,additional challenges will arise in logical computation[58, 59].On the classical side, we must ensure that software elements including our calibration protocols, real-time decoders, and logical compilers can scale to the sizes and complexities needed to run multi-surface-code operations[60].With below-threshold surface codes, we have demonstrated processor performance that can scale in principle, but which we must now scale in practice.

VII Author Contributions

The Google Quantum AI team conceived and designed the experiment. The theory and experimental teams at Google Quantum AI developed the data analysis, modeling and metrological tools that enabled the experiment, built the system, performed the calibrations, and collected the data. All authors wrote and revised the manuscript and the Supplementary Information.

VIII Acknowledgements

We are grateful to S.Brin, S.Pichai, R.Porat, and J.Manyika for their executive sponsorship of the Google Quantum AI team, and for their continued engagement and support.

IX Ethics Declarations

The authors declare no competing interests.

X Additional Information

Supplementary Information is available for this paper.Correspondence and requests for materials should be addressed to H. Neven (neven@google.com).

XI Data Availability

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